XWM8739SEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'XWM8739SEDS/V' PDF : 37 Pages View PDF
WM8739
Production Data
The digital audio interface takes the data from the internal ADC digital filters and places it on
ADCDAT and ADCLRC. ADCDAT is the formatted digital audio data stream output from the ADC
digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that
controls whether Left or Right channel data is present on the ADCDAT line. ADCDAT and ADCLRC
are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. ADCDAT is always an output. BCLK and ADCLRC maybe an input or an output
depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE
OPERATION section.
There are four digital audio interface formats accommodated by the WM8739. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a
ADCLRC transition.
ADCLRC
BCLK
1/fs
LEFT CHANNEL
RIGHT CHANNEL
ADCDAT
123
MSB
n-2 n-1 n
LSB
123
MSB
n-2 n-1 n
LSB
Figure 13 Left Justified Mode
I2S mode is where the MSB is available on the 2nd rising edge of BCLK following an ADCLRC
transition.
1/fs
ADCLRC
LEFT CHANNEL
RIGHT CHANNEL
BCLK
ADCDAT
1 BCLK
123
MSB
n-2 n-1 n
LSB
1 BCLK
123
MSB
n-2 n-1 n
LSB
Figure 14 I2S Mode
Right Justified mode is where the LSB is available on the rising edge of BCLK preceding an ADCLRC
transition, yet MSB is still transmitted first.
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PD, Rev 4.2, July 2008
18
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