XWM8739SEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'XWM8739SEDS/V' PDF : 37 Pages View PDF
WM8739
DIGITAL AUDIO INTERFACE TIMING
Production Data
XTI/MCLK
tXTIL
tXTIH
tXTIY
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
XTI/MCLK System clock pulse width
high
TXTIH
XTI/MCLK System clock pulse width
low
TXTIL
XTI/MCLK System clock cycle time
TXTIY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20
ns
20
ns
50
ns
BCLK
WM8739
ADC ADCLRC
ADCDAT
DSP
ENCODER
Figure 2 Master Mode Connection
BCLK
(Output)
ADCLRC
(Output)
ADCDAT
Figure 3 Digital Audio Data Timing – Master Mode
w
tDL
tDDA
PD, Rev 4.2, July 2008
9
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