Z801808PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z801808PSC' PDF : 85 Pages View PDF
Z80180
Microprocessor Unit
34
DMA Control Signals
ø
DREQi
(at level sense)
DREQi
(at level sense)
TENDi
ST
CPU or DMA READ/WRITE Cycle (Only DMA WRITE Cycle for TENDi)
T1
T2
TW
T3
T1
45 46*1
45 46*2
47
*3 17
*4 18
48
Notes:
1. tDRQS and tDHQH are specified for the rising edge of clock followed by T3.
2. tDRQS and tDHQH are specified for the rising edge of clock.
3. DMA cycle starts.
4. CPU cycle starts.
Figure 19. DMA Control Signals
PS014004-1106
Architecture
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