Z801808PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z801808PSC' PDF : 85 Pages View PDF
Z80180
Microprocessor Unit
40
Channel 1
Mnemonics TDR1 (Address (07h)
76 54 32 1
—- — —- — — — —
ASCI Transmit Channel 1
Figure 29. ASCI Register Channel 1
ASCI Receive Registers
Register addresses 08h and 09h hold the ASCI receive data for channel 0 and channel 1,
respectively.
Channel 0
Mnemonics TSR0 (Address (08h)
ASCI Receive Register Channel 0
76 54 32 1
—— —— — — —
ASCI Receive Data
Figure 30. ASCI Receive Register Channel 0
PS014004-1106
Architecture
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