Z801808VSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z801808VSC' PDF : 85 Pages View PDF
Z80180
Microprocessor Unit
41
Channel 1
Mnemonics TSR1 (Address (09h)
ASCI Receive Register Channel 1R
76 54 32 1
—— —— — — —
ASCI Receive Data
Figure 31. ASCI Receive Register Channel 1R
ASCI Channel Control Register A
ASCI Channel Control Register A
Bit
7
MPE
R/W
ASCI Control Register A 0 (CNTLA0: I/O Address = 00h)
6
5
4
3
2
1
0
MPBR/
RE
TE
RTS0 EFR
MOD2 MOD1 MOD0
R/W
R/W
R/W
R/W
R/W
R/W R/W
Bit
7
MPE
R/W
ASCI Control Register A 1 (CNTLA1: I/O Address = 01h)
6
5
4
3
2
1
RE
TE
__
MPBR/
EFR
MOD2 MOD1
R/W
R/W
R/W
R/W
R/W
R/W
0
MOD0
R/W
Figure 32. ASCI Channel Control Register A
MPE: Multi-Processor Mode Enable (bit 7)—The ASCI features a
multiprocessor communication mode that utilizes an extra data bit for selective
communication when a number of processors share a common serial bus. Multiprocessor
data format is selected when the MP bit in CNTLB is set to 1. If multiprocessor mode is not
selected (MP bit in CNTLB = 0), MPE exhibits no effect. If multiprocessor mode is selected,
MPE enables or disables the wake-up feature as follows.
If MBE is set to 1, only received bytes in which the MPB (multiprocessor bit) = 1 can affect
the RDRF and error flags. Effectively, other bytes (with MPB = 0) are ignored by the ASCI. If
PS014004-1106
Architecture
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