Zilog
TIMER DATA REGISTERS
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
TMDR0L
Read/Write
Addr 0CH
7 6 54 3 21 0
Figure 23. Timer 0 Data Register L
TMDR0H
Read/Write
Addr 0DH
15 14 13 12 11 10 9 8
When Read, read Data Register L
before reading Data Register H.
TMDR1L
Read/Write
Addr 14H
7 6 54 3 21 0
Figure 24. Timer 1 Data Register L
Figure 25. Timer 0 Data Register H
TMDR1H
Read/Write
Addr 15H
15 14 13 12 11 10 9 8
When Read, read Data Register L
before reading Data Register H.
Figure 26. Timer 1 Data Register H
TIMER RELOAD REGISTERS
RLDR0L
Read/Write
Addr 0EH
7 6 54 3 21 0
Figure 27. Timer 0 Reload Register L
RLDR1L
Read/Write
Addr 16H
7 6 54 3 21 0
Figure 28. Timer 1 Reload Register L
RLDR0H
Read/Write
Addr 0FH
15 14 13 12 11 10 9 8
Figure 29. Timer 0 Reload Register H
RLDR1H
Read/Write
Addr 17H
15 14 13 12 11 10 9 8
Figure 30. Timer 1 Reload Register H
3-36
PS009801-0301
DS971820600