Z8018233FSE View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8018233FSE' PDF : 109 Pages View PDF
Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
16550 MIMIC REGISTERS (Continued)
Modem Status Register
Scratch Register
Bit 7 Data Carrier Detect
This bit must be written by the Z180 MPU.
Bit 6 Ring Indicator
This bit must be written by the Z180 MPU.
Bits 7-0 Scratch Register
This register is used by the PC/XT/AT programmer for
temporary data storage. The Z180 MPU is able to read this
register. If the PC/XT/AT writes to this register, no interrupt
to the Z180 MPU is generated.
Bit 5 Data Set Ready
This bit must be written by the Z180 MPU.
Bit 4 Clear to Send
This bit must be written by the Z180™ MPU.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 000000
Divisor Latch (MS)
Bit 3 Delta Data Carrier Detect
This bit is set to 1 whenever the Data Carrier Detect bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
Figure 80. Divisor Latch (LS)
(PC Read/Write, Address 00H and DLAB=1)
(Z180 MPU Read Only, Address xxF8H)
Bit 2 Trailing Edge Ring Indicator
This bit is set to 1 on the falling edge of the Ring Indicator
bit. This bit is reset when the PC/XT/AT reads the Modem
Status Register.
Bit 1 Delta Data Set Ready
This bit is set to 1 whenever the Data Set Ready bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
Bit 0 Delta Clear To Send
This bit is set to 1 whenever the Clear To Send bit changes
state. This bit is reset when the PC/XT/AT reads the Modem
Status Register.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 000000
Divisor Latch (LS)
Bit 7-0 Divisor Latch Most Significant Byte (MS)
This register contains the Low order byte of the Baud rate
divisor. Writing to this register with the PC/XT/AT will
generate an interrupt to the Z180 MPU. It can then read the
Baud rate divisor and set up the application.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 000000
Scratch Register
Figure 81. Divisor Latch (MS)
(PC Read/Write, Address 01H and DLAB=1)
(Z180 MPU Read Only, Address xxF9H)
Divisor Latch (LS)
Figure 79. Scratch Register
(PC Read/Write, Address 07H)
(Z180 MPU Read Only, Address xxF7H)
Divisor Latch (MS)
Bit 7-0 Divisor Latch Most Significant Byte (MS)
This register contains the High order byte of the Baud rate
divisor. Writing to this register with the PC/XT/AT will
generate an interrupt to the Z180 MPU. It can then read the
Baud rate divisor and set up the application.
3-74
PS009801-0301
DS971820600
Share Link: 
