Z8019533FSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8019533FSC' PDF : 95 Pages View PDF
Zilog
PRELIMINARY
Z80185/Z80195
SMART PERIPHERAL CONTROLLERS
Individual Pin Selection Between PIA1 and
CTCs
The assignment of the choice between PIA1 and CTC I/Os
is controlled by the PIA1/CTC Pin Select Register (Figure
79).
Bit 7. Reserved, and should be programmed as 0.
Bits 6-4. When the PIA1 data direction register has set the
corresponding pins as outputs, for each of these bits that
is 0, the pin is driven with the state of the corresponding bit
of the PIA 1 Data register, while for each of these bits that
is 1, the associated pin is driven with the indicated CTC
output. These bits Reset to 0.
Bits 3-1. These bits control whether the CLK/TRG inputs of
CTCs 3-1 are taken from PIA3-1, respectively, or from the
ZC/TO outputs of CTC2-0, respectively. These bits do not
have any affect on the operating mode of the CTCs.
Bit 0. This bit is reserved and should be programmed as
0. CTC0's CLK/TRG0 input is always connected to the
PIA10 pin.
PIA1/CTC Pin Select Register (I/O Address %DE)
765 43210
00 0 0 00 00
Reserved, program as 0.
PIA11/CLKTRG1
1 = CLK/TRG1 = ZC/TO0
0 = CLK/TRG1 = pin
PIA12/CLKTRG2
0 = CLK/TRG2 = ZC/TO1
1 = CLK/TRG2 = pin
PIA13/CLKTRG3
0 = CLK/TRG3 = ZC/TO2
1 = CLK/TRG3 = pin
PIA14/ZCTO1
0 = PIA14
1 = ZC/TO1
PIA15/ZCTO2
0 = PIA15
1 = ZC/TO2
PIA16/ZCTO3
0 = PIA16
1 = ZC/TO3
Reserved, program as 0.
Figure 88. PIA1/CTC Pin Select Register
(I/O Address %DE)
86
DS971850301
Share Link: 
