Z8030 View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8030' PDF : 317 Pages View PDF
SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.2 Z80X30 INTERFACE TIMING (Continued)
2.2.1 Z80X30 Read Cycle Timing
The read cycle timing for the Z80X30 is shown in Figure 2-1.
The register address on AD7-AD0, as well as the state of
/CS0 and /INTACK, are latched by the rising edge of /AS.
R//W must be High before /DS falls to indicate a read
cycle. The Z80X30 data bus drivers are enabled while CS1
is High and /DS is Low.
/AS
/CS0
/INTACK
AD7 - AD0
R//W
Address
Data Valid
CS1
/DS
Figure 2-1. Z80X30 Read Cycle
2-2
UM010901-0601
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