Z8038018FSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8038018FSC' PDF : 115 Pages View PDF
ZILOG
MICROPROCESSOR
EXTERNAL INTERFACE (Continued)
Reset Timing
The timing for entering and exiting the reset state is shown
in Figures 18 and 19. The effects of reset on the internal
state of the Z380 MPU are detailed in the Reset section.
The synchronization of IOCLK at the end of the reset state
is shown in Figure 20. Note that the IOCLK divisor is set to
the maximum value (eight) by /RESET and is only synchro-
nized at the end of the reset state.
BUSCLK
Transaction in progress
T9
TRL
ADDRESS
DATA
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
/IOCTL3-0
/RESET
Figure 18. Reset Entry
PS010001-0301
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