Z8038018FSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8038018FSC' PDF : 115 Pages View PDF
ZILOG
MICROPROCESSOR
Mnemonic
LDDW
LDDRW
Symbolic
Operation
Flags
P/
S Z x Hx VNC
(DE) ← (HL)
• • x 0x V0•
(DE+1) ← (HL+1)
(1)
DE ← DE-2
HL ← HL-2
BC(15-0) ← BC(15-0)-2
(DE) ← (HL)
• •x 0x00•
(DE+1) ← (HL+1)
(2)
DE ← DE-2
HL ← HL-2
BC(15-0) ← BC(15-0)-2
Repeat until BC = 0
Opcode
76 543 210
11 101 101
11 101 000
11 101 101
11 111 000
# of Execute
HEX Bytes Time Notes
ED 1 3+r+w N,L8(4)
E8
ED 1 (3+r+w)nN,L8(4)
F8
r
Reg
000 B
001 C
010 D
011 E
100 H
101 L
111 A
pp Regs
00 BC
00 DE
11 HL
y XY
0 IX
1 IY
Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
L7: In Long Word mode, this instruction exchanges in 32-bits;
src(31-0) ↔ dst(31-0)
L8: In Long Word mode, this instruction transfers in 2 words and BC modified by 4 instead of 2
N: In Native mode, this instruction uses addresses modulo 65536.
(1): P/V flag is 0 if the result of BC-1 = 0, otherwise P/V = 1.
(2): P/V flag is 0 only at completion of instruction.
(3): Z Flag is 1 if A = (HL), otherwise Z = 0
(4): Source, Destination address, count value must be even numbers.
PS010001-0301
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