Z8038018FSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8038018FSC' PDF : 115 Pages View PDF
ZILOG
16/32 BIT ARITHMETIC AND LOGICAL GROUP (Continued)
MICROPROCESSOR
Mnemonic
ADDW [HL,]nn
Symbolic
Operation
HL← HL + nn
ADDW [HL,]XY
HL ← HL+XY
ADDW [HL,](XY+d) HL ← HL+(XY+d)
ADCW [HL,]uu
SUBW [HL,]uu
SBCW [HL,]uu
ANDW [HL,]uu
ORW [HL,]uu
XORW [HL,]uu
CPW [HL,]uu
ADD HL, (nn)
HL ← HL+uu+CY
HL ← HL-uu
HL ← HL - uu - CY
HL ← HL AND uu
HL ← HL OR uu
HL ← HL XOR uu
HL - uu
HL ← HL+(nn)
SUB HL, (nn)
HL ← HL- (nn)
Flags
P/
SZ x Hx VNC
¤ ¤ x ¤ x V0¤
¤ ¤ x ¤ x V0¤
¤ ¤ x ¤ x V0¤
¤ ¤ x ¤ x V0¤
¤ ¤ x ¤ x V1¤
¤ ¤ x ¤ x V1¤
¤ ¤ x 1x P00
¤ ¤ x 0x P00
¤ ¤ x 0x P00
¤ ¤ x ¤ x V1¤
• • x ¤ x • 0¤
• • x ¤ x • 0¤
Opcode
# of Execute
76 543 210 HEX Bytes Time Notes
11 101 101 ED 4 2
I
10 (000) 110 86
← n →
← n →
11 y11 101
22
I
10 (000) 111 87
11 y11 101
4 4+r
I
11 (000) 110 C6
(001)
(010)
(011)
(100)
(110)
(101)
(111)
11 101 101 ED 4 2+r
11 010 110 C6
← n →
← n →
11 101 101 ED 4 2+r
11 010 110 D6
← n →
← n →
I, X1
I, X1
uu is any of rr, nn, t, (IX+d), (IY+d) as shown for ADDW instruction. The indicated bits replace the (000) is the ADD set
above.
dd Pair
00 BC
01 DE
10 HL
11 SP
pp Pair
00 BC
01 DE
11 HL
qq
Pair
00
BC
01
DE
11
SP
y
XY
0
IX
1
IY
Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I: This instruction may be used with DDIR Immediate instructions.
X1: In Extend mode, this instruction operates in 32-bits;
src(31-0) ← src(31-0) opr dst(31-0)
PS010001-0301
Share Link: 
