Z80C3010PEC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z80C3010PEC' PDF : 96 Pages View PDF
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Internal Data Bus
CPU/I/O
I/O Data buffer
BRG
Input
Upper Byte (WR13) Lower Byte (WR12)
Time Constant
Time Constant
16-Bit Down Counter
DIV 2
Status FIFO
10 X 19 Frame
Rec. Error FIFO
3 Byte Deep
Rec. Error FIFO
3 Byte Deep
BRG
Output
14-Bit Counter
Hunt Mode (BISYNC)
Rec. Error Logic
DPLL
IN
DPLL
DPLL
OUT
Internal TXD
SYNC Register
& Zero Delete
3-Bit
Receive Shift
Register
RXD
1-Bit
MUX
NRZI Decode
MUX
To Transmit Section
SDLC-CRC
CRC Delay
Register (8 bits)
CRC
Checker
SYNC
CRC
CRC Result
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