Z86228 View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86228' PDF : 7 Pages View PDF
PRELIMINARY
DC CHARACTERISTICS
TA = 0°C to +70°C; VCC = +4.75V to +5.25V
Sym
V
IL
VIH
V
OL
Parameter
Input Voltage Low
Input Voltage High
Output Voltage Low
VOH
Output Voltage High
I
Input Leakage
IL
ICC
Supply Current
Notes:
[1] Pin 13 (HLF)
[2] Pin 17 (CT/SDA) is Open-Drain.
[3] VDD Digital + VDD Analog combined.
Min
0
0.7VCC
VCC–0.4
–.0
Max
0.2V
CC
VCC
0.4
1
3.0
25
Units
V
V
V
V
V
µA
mA
Z86228
CPS DC-4243-00
Conditions
I = 1.00 mA
OL
IOL = 50 µA [1]
IOH = 0.75 mA [2]
0V, V
CC
[3]
AC AND TIMING CHARACTERISTICS*
(Reference Line 21 AC/DC Timing)
Composite Video Input
Amplitude:
Polarity:
Bandwidth
1.0 V p-p, ± 3 dB
Sync tips negative
600 kHz
Horizontal Signal Input (preferably H Flyback)
Amplitude:
Polarity:
Frequency:
CMOS level signal, Low ≤ 0.2VCC, High ≥ 0.7VCC
Any
15,734.263 Hz, ± 3%
Line 211 Input Parameters (at 1.0 V p-p)
Code Level:
50 IRE ± 10 IRE
Clock Run-in Start 2: 10.5 µs, ± 0.5µs
Input Signal-to-Random Noise Performance
Unit will function down to a 25 dB ratio (CCIR weighted) with one error per row or better at that level.
Internal Sync Circuits
The internal sync circuits will lock to all 525 line signals having a vertical sync pulse that meets the following conditions:
s It is at least 2.5H long.
s It starts at the proper 2H boundary for its field.
s If equalizing pulse serrations are present they must be less than 0.125H in width.
Timing Signals
Dot Clock:
Dot Period:
Character Cell Width:
Width of Row (Box):
Width of Row (Char):
768 x FH = 12.0839 MHz
82.75 nsec
1.324 µsec
45.018 µsec
42.370 µsec
*All values are nominal and not fully characterized.
4
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