Z8674312PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8674312PSC' PDF : 84 Pages View PDF
CMOS Z8® OTP Microcontrollers
Product Specification
61
Table 22. Stop Mode Recovery Source
D4 D3 D2 SMR Source selection
0
0
0
POR recovery only
0
0
1
P30 transition
0
1
0
P31 transition (Not in analog mode)
0
1
1
P32 transition (Not in analog mode)
1
0
0
P33 transition (Not in analog mode)
1
0
1
P27 transition
1
1
0
Logical NOR of Port 2 bits 0-3
1
1
1
Logical NOR of Port 2 bits 0-7
Stop Mode Recovery Delay Select (D5). The 5 ms RESET delay after Stop Mode Recov-
ery is disabled by programming this bit to a zero. A “1” in this bit will cause a 5 ms
RESET delay after Stop Mode Recovery. The default condition of this bit is 1. If the fast
wake up mode is selected, the Stop Mode Recovery source needs to be kept active for at
least 5TpC.
Stop Mode Recovery Level Select (D6). A “1” in this bit defines that a high level on any
one of the recovery sources wakes the MCU from STOP Mode. A 0 defines low level
recovery. The default value is 0.
Cold or Warm Start (D7). This bit is set by the device upon entering STOP Mode. A “0”
in this bit indicates that the device has been reset by POR (cold). A “1” in this bit indicates
the device was awakened by a SMR source (warm).
Stop Mode Recovery Register 2 (SMR2). This register contains additional Stop Mode
Recovery sources. When the Stop Mode Recovery sources are selected in this register then
SMR Register Bits D2, D3, and D4 must be 0.
SMR:10
D1 DO
0
0
0
1
1
0
Operation
Description of Action
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
Watchdog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer
that resets the Z8 if it reaches its terminal count. The WDT is disabled after Power-On
PS022901-0508
Electrical Characteristics
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