Z86C3416PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86C3416PSC' PDF : 70 Pages View PDF
ZiLOG
DR
0
1
Sampling Clock
Divide by 16
Divide by 64
Bit 2,1 are the Clock Source and Speed Select
When the BRG mode bit in the ASEXT register is set to 0,
these 3 bits, along with DR and PR in this register define
the ASCI baud rate. Bits 2, 1 and 0 specify a power-of-two
divider of the SCLK as defined in Table 22. These bits
should never be set to all 1s or erratic results may occur.
See the Baud Rate Generation Summary for more informa-
tion on setting the ASCI baud rate.
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
Table 22. Clock Source and Speed Bits
SS2
SS1
SS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Divider (DIV)
÷1
÷2
÷4
÷8
÷16
÷32
÷64
Reserved
DS007601-Z8X0499
PRELIMINARY
51
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