Z86C4416PSC View Datasheet(PDF) - Zilog

Part Name

Description

MFG CO.

Z86C4416PSC

CMOS Z8® MCUS WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY

Zilog

'Z86C4416PSC' PDF : 70 Pages View PDF

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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
ASCI STATUS REGISTER (STAT) (Continued)
Table 27. Baud Rate List (BRG Mode = 0)
Prescaler
Sampling
Rate
Divide
PS Ratio DR Rate SS2
0
0
0
0
16
0
1
1
0
SCLK
÷ 10
1
0
0
0
1
64
0
1
1
1
0
0
0
0
16
0
1
1
1
SCLK
÷ 30
1
0
0
0
1
64
0
1
1
1
Baud Rate
SS1 SS0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
Divide
Ratio
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷1
÷2
÷4
÷8
÷16
÷32
÷64
General
Divide Ratio
SCLK ÷ 160
SCLK ÷ 320
SCLK ÷ 640
SCLK ÷ 1280
SCLK ÷ 2560
SCLK ÷ 5120
SCLK ÷ 10240
SCLK ÷ 640
SCLK ÷ 1280
SCLK ÷ 2560
SCLK ÷ 5120
SCLK ÷ 10240
SCLK ÷ 20480
SCLK ÷ 40960
SCLK ÷ 480
SCLK ÷ 960
SCLK ÷ 1920
SCLK ÷ 3840
SCLK ÷ 7680
SCLK ÷ 15360
SCLK ÷ 30720
SCLK ÷ 1920
SCLK ÷ 3840
SCLK ÷ 7680
SCLK ÷ 15360
SCLK ÷ 30720
SCLK ÷ 61440
SCLK ÷ 122880
Example Baud Rate (bps)
SCLK = SCLK = SCLK =
6.144 4.608 3.072
MHz MHz MHz
38400
19200
9600
4800
2400
1200
600
9600
4800
2400
1200
600
300
150
4800
2400
1200
600
300
150
75
2400
1200
600
300
150
75
37.5
19200
9600
4800
2400
1200
600
300
4800
2400
1200
600
300
150
75
56
PRELIMINARY
DS007601-Z8X0499

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