Z86E08SL1995 View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86E08SL1995' PDF : 38 Pages View PDF
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
17
6. After a delay of at least 1µs minimum from VPP rising, OE is raised to VIH.
7. The CLOCK is raised to VIH.
8. OE is pulsed Low to VIL, then High to VIH.
9. The CLOCK is lowered to VIL.
10. Repeat steps 7 to 9 six more times.
11. After a delay of at least 1µs minimum, EPM is raised to VIH.
12. The device is now in OPTION BIT READ/WRITE mode. See Figure 11.
Figure 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Functional Timing
VCC
5V
0V
CLEAR
VIH
V IL
EPM
VIH
V IL
CE
VIH
V IL
VPP
VIH
V IL
CLOCK VIH
V IL
OE
VIH
V IL
PGM
VIH
V IL
Data
(Port 2)
XOUT
Not connected
Not connected
Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions
EPROM Signal
D0–D3
D4–D7
GND
VCC
18-Pin DIP/SOIC
Pins 15, 16, 17, 18
Pins 1, 2, 3, 4
Pin 14
Pin 5
20-Pin SSOP
Pins 17, 18, 19, 20
Pins 1, 2, 3, 4
Pins 15, 16
Pins 5, 6
Forced State
NC
NC
GND
5V
PS009201-0301
Programming Specification
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