Z86E3412PEC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86E3412PEC' PDF : 84 Pages View PDF
CMOS Z8® OTP Microcontrollers
Product Specification
41
Port 1 can be placed in the high-impedance state along with Port 0, AS, DS, and R/W,
allowing the Z86E43/743/E44 to share common resources in multiprocessor and DMA
applications. In ROM mode, Port 1 is defined as input after reset.
MCU
Port 2 (I/O)
Handshake Controls
DAV1 and RDY1
(P33 and P34)
Open Drain
Open
PAD
Out
1.5
In
2.3 Hysteresis
R ~~500 kΩ
Auto Latch
Figure 19. Port 1 Configuration (Z86E43/743/E44 Only)
Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port. These
eight I/O lines can be configured under software control as an input or output, indepen-
dently. All input buffers are Schmitt-triggered. Bits programmed as outputs can be glo-
bally programmed as either push-pull or open-drain. Low EMI output buffers can be
globally programmed by the software. When used as an I/O port, Port 2 can be placed
under handshake control. After reset, Port 2 is defined as an input.
PS022901-0508
Electrical Characteristics
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