Z86E72 View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86E72' PDF : 74 Pages View PDF
Z86E72/E73
OTP IR Microcontrollers
EPROM PROGRAMMING
Table 10. Programming and Testmode
Device Pins
User/Test Mode
Device Pin #
P33
P32 Pref1 P31 P20
User Modes
VPP
EPM
/CE
/OE /PGM Addr
EPROM Read
VCC
VH
VIL
VIL
VIH
Addr
Program
VPP
VCC
VIL
VIH
VIL
Addr
Program Verify
VPP
VCC
VIL
VIL
VIH
Addr
RC Option
VPP
VCC
VH
VIH
VIL
XX
Margin Read
VVA
VH
VIL
VH
VIH
Addr
Shadow Row Rd VCC
VH
VIL
VIL
VIH
COL
Shadow Row Prg VPP
VH
VIL
VIH
VIL
COL
Shadow Row Ver VPP
VH
VIL
VIL
VIH
COL
Shadow Col Rd
VCC
VH
VIL
VIL
VIH
ROW
Shadow Col Prg
VPP
VH
VIL
VIH
VIL
ROW
Shadow Col Ver
VPP
VH
VIL
VIL
VIH
ROW
Page Prg 2 Byte
VPP
VH
VIL
VIH
VIL
TBD
Page Prg 4 Byte
VPP
VH
VIL
VIH
VIL
TBD
Page Prg 8 Byte
VPP
VH
VIL
VIH
VIL
TBD
Page Prg 16 Byte VPP
VH
VIL
VIH
VIL
TBD
Notes:
1. All test modes are entered by first setting up the corresponding test
address and then latching the address by bringing the /OE to VH and then
to VIL, except for the margin read which requires /OE to be kept at VH.
VVA = Variable from VCC to VPP
VPP = 12.5V ± 0.5V
VH = 12.5V ± 0. 5V
VIH = 3V
VIL = 0V
XX = Irrelevant
IPP during programming = 40 mA maximum
ICC during programming, verify, or read = 40 mA maximum.
VCC
3.0V
6.0V
6.0V
6.0V
6.0V
3.0V
6.0V
6.0V
3.0V
6.0V
6.0V
6.0V
6.0V
6.0V
6.0V
Port 1
CNFG
DATA
Out
In
Out
XX
Out
Out
In
Out
Out
In
Out
In
In
In
In
Test
ADDR
A0-A3
XX
XX
XX
XX
00
01
01
01
02
03
02
04
05
06
07
Note
1
1
1
1
1
1
1
1
1
1
1
1-56
PRELIMINARY
DS96LVO1100
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