Z86E72/E73
OTP IR Microcontrollers
Z8® STANDARD CONTROL REGISTER DIAGRAMS (Continued)
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Reserved (Must be 0)
Figure 61. Interrupt Priority Registers
((0) F9H: Write Only)
R250 IRQ
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16
IRQ4 = T8
Default Setting After Reset = 0000 0000
Reserved (Must be 0)
Inter Edge
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
Figure 62. Interrupt Request Register
((0) FAH: Read/Write)
R251 IMR
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
1 Enables IRQ4-IRQ0
(D0 = IRQ0)
Reserved (Must be 0)
Reserved (Must be 0)
0 Master Interrupt Disable*
1 Master Interrupt Enable
Figure 63. Interrupt Mask Register
((0) FBH: Read/Write)
R252 Flags
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Tag
Sign Flag
Zero Flag
Carry Flag
Figure 64. Flag Register
((0) FCH: Read/Write
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Default Setting After
Reset = 0000
Expanded Register (Bank)
Pointer
Working Register
Pointer
Figure 65. Register Pointer
((0) FDH: Read/Write)
1-70
PRELIMINARY
DS96LVO1100