Z86K1605PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86K1605PSC' PDF : 24 Pages View PDF
Zilog
Z86K13/K14/K15/K16/K17/K18
CMOS Z8® 8-Bit MCU Keyboard Controllers
Watch-Dog Timer. The Watch-Dog Timer is activated au- power-up of the Z86K15 (the default upon power-up is 0).
tomatically by power-on if it is enabled in the Mask Option. A hot start occurs when a WDT time-out has occurred (bit
1 The WDT is a retriggerable one-shot timer that resets the 7 is set to 1). Bit 7 of the IRQ register is read-only and is
Z8 if it reaches its terminal count. The WDT is driven by the automatically reset to 0 when read.
system clock. It must be refreshed at least once during
each time cycle by executing the WDT instruction. WDT
can be enabled by Mask Option. (Figure 18)
Watch-Dog Timer . The WDT time-out is 2----9---4-f--(9--H--1---z2---)-m-----s--.
WDT During HALT (D5-R250). This bit determines wheth-
WDT Hot bit. Bit 7 of the Interrupt Request register (IRQ er or not the WDT is active during HALT Mode. The default
register FAH) determines whether a hot start or cold start is 1, and a 1 indicates active during HALT.
occurred. A cold start is defined as reset occurring from
VCC
Internal
Reset
18 Tpc
POR
Reset
Delay
* Reset Delay = POR 147 ms ±10% at 4 MHz.
Figure 18. WDT Turn-On Timing After Reset
DS97KEY0204
PRELIMINARY
17
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