Z86L7808PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86L7808PSC' PDF : 59 Pages View PDF
Zilog
Z86L78
IR/Low-Voltage Microcontroller
CTR1 Register Description
In Demodulation Mode, this bit is set to 1 when a rising
Mode. If it is 0, the Counter/Timers are in the transmit
mode, otherwise they are in the demodulation mode.
edge is detected in the input signal. In order to reset it, a 1
should be written to this location.
1
P36_Out/Demodulator_Input. In Transmit Mode, this bit
defines whether P36 is used as a normal output pin or the
combined output of T8 and T16.
Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0,
the output of T16 is set to 0 when it starts to count. If it is
1, the output of T16 is set to 1 when it starts to count. This
bit is effective only in Normal or Ping-Pong Mode (CTR1,
In Demodulation Mode, this bit defines whether the input
signal to the Counter/Timers is from P20 or P31.
D3, D2). When this bit is set, T16_OUT will be set to the
opposite state of this bit. This insures that when the clock
is enabled a transition occurs to the initial state set by
T8/T16_Logic/Edge _Detect. In Transmit Mode, this field CTR1, D0.
defines how the outputs of T8 and T16 are combined
(AND, OR, NOR, NAND).
In Demodulation Mode, this bit is set to 1 when a falling
edge is detected in the input signal. In order to reset it, a 1
In Demodulation Mode, this field defines which edge should be written to this location.
should be detected by the edge detector.
Note: Modifying CTR1, (D1 or D0) while counters are en-
Transmit_Submode/Glitch Filter. In Transmit Mode, this abled will cause un-predictable output from T8/16_out.
field defines whether T8 and T16 are in the "Ping-Pong"
mode or in independent normal operation mode. Setting
this field to "Normal Operation Mode" terminates the "Ping-
Pong Mode" operation. When set to 10, T16 is immediately
forced to a 0.
In Demodulation Mode, this field defines the width of the
glitch that should be filtered out.
Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the
output of T8 is set to 0 when it starts to count. If 1, the out-
put of T8 is set to 1 when it starts to count. When this bit is
set to 1 or 0, T8_OUT will be set to the opposite state of
this bit. This insures that when the clock is enabled a tran-
sition occurs to the initial state set by CTR1, D1.
DS97LVO0701
2-27
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