Z86L8008SSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86L8008SSC' PDF : 58 Pages View PDF
Zilog
Z86L79/80
Low-Voltage Microcontroller
PCON (FH) 00H
1
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
Figure 33. Port Configuration Register (PCON)
(Write Only)
Comparator Output Port 3 (D0). Bit 0 controls the com-
parator used in Port 3. A 1 in this location brings the com-
parator outputs to P34 and P37, and a 0 releases the Port
to its standard I/O configuration.
Stop-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 34). All bits are write only ex-
cept bit 7, which is read only. Bit 7 is a flag bit that is hard-
ware set on the condition of STOP recovery and reset by
a power-on cycle. Bit 6 controls whether a low level or a
high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits 2, 3, and 4, the
SMR register, specify the source of the Stop-Mode Recov-
ery signal. Bits 0 and 1 determine the frequency of
SCLK/TCLK in relation to the OSC. The SMR is located in
Bank F of the Expanded Register Group at address 0BH.
PRELIMINARY
3-41
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