Z89139 View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z89139' PDF : 66 Pages View PDF
Zilog
Z89138/Z89139
Voice Processing Controllers
Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS For external memory references, Port 0 provides address
compatible port. These eight I/O lines are configured un- bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib-
1 der software control as a nibble I/O port, or as an address ble) depending on the required address space. If the ad-
port for interfacing external memory. The input buffers are dress range requires 12 bits or less, the upper nibble of
Schmitt-triggered and the output drivers are push-pull. Port 0 can be programmed independently as I/O while the
Port 0 is placed under handshake control. In this configu- lower nibble is used for addressing. If one or both nibbles
ration, Port 3, lines P32 and P35 are used as the hand- are needed for I/O operation, they are configured by writ-
shake control /DAV0 and RDY0. Handshake signal direc- ing to the Port 0 mode register.
tion is dictated by the I/O direction to Port 0 of the upper
nibble P07-P04. The lower nibble must have the same di- In ROMless mode, after a hardware reset, Port 0 is config-
rection as the upper nibble.
ured as address lines A15-A8, and extended timing is set
to accommodate slow memory access. The initialization
The Auto Latch on Port 0 puts valid CMOS levels on all routine can include reconfiguration to eliminate this ex-
CMOS inputs which are not externally driven. Whether this tended timing mode. (In ROM mode, Port 0 is defined as
level is 0 or 1 cannot be determined. A valid CMOS level, input after reset.)
rather than a floating node, reduces excessive supply cur-
rent flow in the input buffer.
Port 0 is set in the high-impedance mode if selected as an
address output state along with Port 1 and the control sig-
nals /AS, /DS, and R//W (Figure 11).
4
Z89138/139
MCU
4
Port 0
(I/O or A15 - A8)
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
OEN
Pad
Out
1.5
2.3V Hysteresis
In
R = 500 KΩ
Auto Latch
Figure 11. Port 0 Configuration
DS97TAD0201
PRELIMINARY
23
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