Z89139 View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z89139' PDF : 66 Pages View PDF
Zilog
Z89138/Z89139
Voice Processing Controllers
WDT Time Select (D0, D1). These bits selects the WDT WDT During HALT (D2). This bit determines whether or
time period. The configuration is shown in Table 10.
not the WDT is active during HALT Mode. A 1 indicates ac-
Table 10. WDT Time Select
Time-out of
Time-out of
D1
D0‘ Internal RC OSC XTAL Clock
tive during HALT. The default is 1.
1
WDT During STOP (D3). This bit determines whether or
not the WDT is active during STOP Mode. Since XTAL
clock is stopped during STOP Mode, the on-board RC
0
0
0
1
5 ms min
15 ms min
256 TpC
512 TpC
must be selected as the clock source to the POR counter.
A 1 indicates active during STOP. The default is 1.
1
0
25 ms min
1024 TpC
1
1
100 ms min
4096 TpC
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
Notes:
TpC = XTAL clock cycle.
Tolerance = ±10%
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configu-
ration of this bit is 0 which selects the RC oscillator.
/RESET
4 Clock
Filter
Clear
CLK
18 Clock RESET
Generator
RESET
WDT Select
(WDTMR)
CK Source
Select
(WDTMR)
XTAL
WDT TAP SELECT
RC
OSC.
5 ms POR 5 ms 15 ms 25 ms 100 ms
M
U
X
CK
WDT/POR Counter Chain
CLR
VDD
2V REF.
2V Operating
+ Voltage Det.
-
From Stop
Mode
Recovery
Source
12 ns Glitch Filter
WDT
Stop Delay
Select (SMR)
Figure 30. Resets and WDT
Internal
RESET
DS97TAD0201
PRELIMINARY
41
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