Z8E00110PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8E00110PSC' PDF : 46 Pages View PDF
ZiLOG
Z8E001
Z8Plus OTP Microcontroller
Z8PLUS CORE
The Z8E001 is based on the ZiLOG Z8Plus Core Architec-
ture. This core is capable of addressing up to 64KBytes of
program memory and 4KBytes of RAM. Register RAM is
accessed as either 8 or 16 bit registers using a combination
of 4, 8, and 12 bit addressing modes. The architecture sup-
ports up to 15 vectored interrupts from external and internal
sources. The processor decodes 44 CISC instructions using
six addressing modes. See the Z8Plus UserÕs Manual for
more information.
RESET
This section describes the Z8E001 reset conditions, reset
timing, and register initialization procedures. Reset is gen-
erated by the Reset Pin, Watch-Dog Timer (WDT), and
Stop-Mode Recovery (SMR).
A system reset overrides all other operating conditions and
puts the Z8E001 into a known state. To initialize the chipÕs
internal logic, the RESET input must be held Low for at
least 30 XTAL clock cycles. The control registers and ports
are reset to their default conditions after a reset from
the RESET pin. The control registers and ports are not reset
to their default conditions after wakeup from Stop Mode or
WDT timeout.
During RESET, the program counter is loaded with 0020H.
I/O ports and control registers are configured to their default
reset state. Resetting the Z8E001 does not affect the con-
tents of the general-purpose registers.
RESET PIN OPERATION
The Z8E001 hardware RESET pin initializes the control
and peripheral registers, as shown in Table 4. Specific reset
values are shown by 1 or 0, while bits whose states are un-
changed or unknown from Power-Up are indicated by the
letter U.
RESET must be held Low until the oscillator stabilizes, for
an additional 30 XTAL clock cycles, in order to be sure that
the internal reset is complete. The RESET pin has a Schmitt-
Trigger input with a trip point. There is no High side pro-
tection diode. The user should place an external diode from
RESET to VCC. A pull-up resistor on the RESET pin is ap-
proximately 500 KΩ, typical.
Program execution starts 10 XTAL clock cycles after RE-
SET has returned High. The initial instruction fetch is from
location 0020H. Figure 9 indicates reset timing.
After a reset, the first routine executed must be one that ini-
tializes the TCTLHI control register to the required system
configuration, followed by initialization of the remaining
control registers.
Table 4. Control and Peripheral Registers
Bits
Register (HEX) Register Name 7 6 5 4 3 2 1 0 Comments
FF
FE
FD
FC
FB
FA
F9ÐF0
EFÐE0
DFÐD8
Stack Pointer
0 0 U U U U U U Stack pointer is not affected by
RESET
Reserved
Register Pointer U U U U 0 0 0 0 Register pointer is not affected by
RESET
Flags
UUUUUU *
* Only WDT & SMR flags are affected
by RESET
Interrupt Mask
0 0 0 0 0 0 0 0 All interrupts masked by RESET
Interrupt Request 0 0 0 0 0 0 0 0 All interrupt requests cleared by
RESET
Reserved
Virtual Copy
Virtual Copy of the Current Working
Register Set
Reserved
DS001101-Z8X0400
PRELIMINARY
15
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