Z8E00110PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8E00110PSC' PDF : 46 Pages View PDF
ZiLOG
Z8E001
Z8Plus OTP Microcontroller
Note: The preceding result does not necessarily reflect the ac-
tual output value. If an external error is holding an output
pin either High or Low against the output driver, the soft-
ware read returns the required value, not the actual state
caused by the contention. When a bit is defined as an out-
put, the Schmitt-trigger on the input is disabled to save
power.
Updates to the output register takes effect based upon the
timing of the internal instruction pipeline, but is referenced
to the rising edge of the clock. The output register can be
read at any time, and returns the current output value that
is held. No restrictions are placed on the timing of reads
and/or writes to any of the port registers with respect to the
others; however, care should be taken when updating the
directional control and special function registers.
When updating a Directional Control Register, the Special
Function Register should first be disabled. If this precaution
is not taken, spurious events could take place as a result of
the change in port I/O status. This precaution is especially
important when defining changes in Port B, as the spurious
event referred to above could be one or more interrupts.
Clearing of the SFR register should be the first step in con-
figuring the port, while setting the SFR register should be
the final step in the port configuration process. To ensure
deterministic behavior, the SFR register should not be writ-
ten until the pins are being driven appropriately, and all ini-
tialization has been completed.
PORT A
Port A is a general-purpose port. Figure 26 features a block
diagram of Port A. Each of its lines can be independently
programmed as input or output via the Port A Directional
Control Register (PTADIR at 0D2H) as seen in Figure 27.
A bit set to a 1 in PTADIR configures the corresponding
bit in Port A as an output, while a bit cleared to 0 configures
the corresponding bit in Port A as an input.
The input buffers are Schmitt-triggered. Bits programmed
as outputs can be individually programmed as either push-
pull or open drain by setting the corresponding bit in the
Special Function Register (PTASFR, Figure 27).
Register 0D2H
PTADIR Register
D7 D6 D5 D4 D3 D2 D1 D0
1 = Output
0 = Input
Figure 26. Port A Directional Control Register
PTASFR.bitN
N = 0...7
PTADIR.bitN
N = 0...7
PA0ÐPA7
PIN
PTAOUT.bitN
N = 0...7
PTAIN.bitN
N = 0...7
Figure 27. Port A Configuration with Open-Drain Capability and Schmitt-Trigger
DS001101-Z8X0400
PRELIMINARY
31
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