Z8F012APB020EG View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8F012APB020EG' PDF : 282 Pages View PDF
Z8 Encore! XP® F082A Series
Product Specification
112
Table 64. UART Control 1 Register (U0CTL1)
Bit
Field
RESET
R/W
Address
7
MPMD[1]
0
R/W
6
MPEN
0
R/W
5
MPMD[0]
0
R/W
4
3
MPBT DEPOL
0
0
R/W
R/W
F43H
2
BRGCTL
0
R/W
1
RDAIRQ
0
R/W
0
IREN
0
R/W
Bit
[7,5]ï€
MPMD[1,0]
[6]ï€
MPEN
[4]ï€
MPBT
[3]ï€
DEPOL
Description
MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) Mode is enabled:
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches the
value stored in the Address Compare Register and on all successive data bytes until
an address mismatch occurs.
11 = The UART generates an interrupt request on all received data bytes for which the most
recent address byte matched the value in the Address Compare Register.
MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) Mode. ï€
0 = Disable MULTIPROCESSOR (9-bit) Mode.ï€
1 = Enable MULTIPROCESSOR (9-bit) Mode.
Multiprocessor Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) Mode is enabled. The 9th bit is
used by the receiving device to determine if the data byte contains address or data informa-
tion.ï€
0 = Send a 0 in the multiprocessor bit location of the data stream (data byte).ï€
1 = Send a 1 in the multiprocessor bit location of the data stream (address byte).
Driver Enable Polarity
0 = DE signal is Active High.ï€
1 = DE signal is Active Low.
PS022827-1212
PRELIMINARY
UART Control Register Definitions
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