Z8F081A View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8F081A' PDF : 282 Pages View PDF
Z8 Encore! XP® F082A Series
Product Specification
57
Architecture
Figure 8 displays the interrupt controller block diagram.
Port Interrupts
Internal Interrupts
High
Priority
Medium
Priority
Vector
Priority
Mux
IRQ Request
Low
Priority
Figure 8. Interrupt Controller Block Diagram
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 57
Interrupt Vectors and Priority: see page 58
Interrupt Assertion: see page 58
Software Interrupt Assertion: see page 59
Watchdog Timer Interrupt Assertion: see page 59
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts. Interrupts are globally enabled by any of the following actions:
• Execution of an EI (Enable Interrupt) instruction
• Execution of an IRET (Return from Interrupt) instruction
PS022827-1212
PRELIMINARY
Architecture
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