Z8L18008PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8L18008PSC' PDF : 70 Pages View PDF
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
T1
T2
TW
ø
49
E
(Memory Read//Write)
49
E
(I/O Read)
49
E
(I/O Write)
D0 - D7
TW
T3
50
50
50
15
16
Figure 24. E Clock Timing
(Memory Read/Write Cycle, I/O Read/Write Cycle)
ø
E
49
50
BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode
Figure 25. E Clock Timing
(BUS RELEASE Mode, SLEEP Mode, SYSTEM STOP Mode)
T2
E
Example
I/O read
→ Opcode fetch
TW
T3
50
49
51
T1
50 52
54
T2
49
53
53
54
Figure 26. E Clock Timing
(Minimum timing example of PWEL and PWEH)
Zilog
1-32
PRELIMINARY
DS971800401
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