Z8L18033PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8L18033PSC' PDF : 70 Pages View PDF
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
T1
T2
T3
T1
T2
T3
φ
/WR
/M1
Write into OMCR
Opcode Fetch
Figure 10. M1 Temporary Enable Timing
Zilog
IOC. This bit controls the timing of the /IORQ and /RD sig- When /IOC=1, the /IORQ and /RD signals function the
nals. It is set to 1 by reset.
same as the Z64180 (Figure 11).
T1
φ
/IORQ
/RD
T2
TW
T3
/WR
Figure 11. I/O Read and Write Cycles with IOC = 1
When /IOC = 0, the timing of the /IORQ and RD signals go active as a result of the rising edge of T2. (Figure 12.)
match the timing of the Z80. The /IORQ and /RD signals
T1
φ
/IORQ
/RD
/WR
T2
TW
T3
Figure 12. I/O Read and Write Cycles with IOC = 0
1-16
PRELIMINARY
DS971800401
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