Z80382/Z8L382
High-Performance Data Communications Processors
AC CHARACTERISTICS (Continued)
RxC(1)
(output)
RXD
t110
t112
t111
Note 1. Receive clock sampling edge is configurable by means of RIRn[6]. See Z80382 User Manual.
Figure 18. HDLC Receive Timing (Full Time HDLC, RxC Output)
Zilog
24
PRELIMINARY
DS97Z382000