Functional Description
The ASM2P5T9070A 2.5V single data rate (SDR) clock buffer is a single-ended input to ten single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single input to ten singleended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network.
Features
• Optimized for 2.5V LVTTL
• Guaranteed Low Skew < 25pS (max)
• Very low duty cycle distortion < 300pS (max)
• High speed propagation delay < 2nS. (max)
• Up to 200MHz operation
• Very low CMOS power levels
• Hot Insertable and over-voltage tolerant inputs
• 1:10 fanout buffer
• 2.5V Supply Voltage
• Available in TSSOP Package
Applications:
ASM2P5T9070A is targeted towards Clock and signal
distribution applications.