AZ100ELT23(2012) Datasheet PDF - AZ Microtek

DESCRIPTION
The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate design of the AZ100ELT23 makes it ideal for applications that require the translation of a clock and a data signal.

FEATURES
• 3.5ns typical propagation delay
• <500ps typical output to output skew
• Differential PECL inputs
• Flow through pinouts
• CMOS/TTL outputs

APPLICATIONS
• LVPECL to LVCMOS/LVTTL translations
• PECL to CMOS/TTL translations