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CDP68HC68S1 Datasheet PDF - Intersil

CDP68HC68S1 image

Part Name
CDP68HC68S1

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page
14 Pages

File Size
72.5 kB

MFG CO.
Intersil
Intersil Intersil

Description
The CDP68HC6SS1 Serial Bus Interface Chip (SBlC) provides a means of interfacing in a Small Area Network configuration, various microcomputers (MCU’s) containing serial ports. Such MCU’s include the family of 68HC05 microcontrollers. The SBlC provides a connection from an MCU’s Serial Communication Interface (asynchronous UART type interface) or Serial Peripheral Interface (synchronous) to a medium speed asynchronous two wire differential signal bus designed to minimize electro magnetic interference. This two wire bus forms the network bus to which all MCU’s are connected (through SBI chips). See Figure 1. Each MCU operates independently and may be added or deleted from the bus with little or no impact on bus operation. Such a bus is ideal for inter-microcomputer communication in hazardous electrical environments such as automobiles, aircraft or industrial control systems.


FEATUREs
• Differential Bus for Minimal EMl
• High Common Mode Noise Rejection
• Ideal for Twisted Pair Wiring
• Data Collision Detection
• Bus Arbitration
• Idle Detection
• Programmable Clock Divider
• Power-On Reset

 


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