CS19233 Datasheet PDF - Applied Micro Circuits Corporation

Overview
   The S19233 can be used to implement the front end of SONET/SDH/FEC/10GbE/FC/G.709 equipment which consists primarily of the serial transmit interface and the serial receive interface. The system timing circuitry consists of a high-speed phase detector, clock and data recovery unit and equalization circuitry. The device utilizes on-chip clock recovery PLL components that allow the use of a slower external clock reference, 155.52 MHz (or equivalent FEC/10GbE/10 Gbps FC rate), in support of existing system clocking schemes.

FEATUREs
• Complies with ITU-T specifications, 50 mUIpp
   max. jitter generation (50 KHz - 80 MHz)
• Complies with XFP MSA Specifications
• 25 mUI
   pp Jitter Generation
• CML serial input sensitivity at 5 mVpp Diff.
• Dual CDR - 9.95 to 11.32 Gbps operation
• Superior Crosstalk Isolation
• Electronic Dispersion Compensation (EDC)
   Optimized for 0 to 100 Km SMF with 2 dB dispersion penalty
• Low power EDC ideal for Power Level 2 XFP
   modules
• Suitable for low Optical Signal to Noise Ratio
   (OSNR) environments
• Automatic Threshold Adjust
• External threshold & Phase Adjust
• AGC embedded equalizer
• LOS Function - Compliant to GR-253
• Integrated equalizer that support over 24” FR-
   4 on Transmitter Electrical Side
• Transmitter (Optical Side) - CDR
• Lock detect indication
• 650 mW Typical Power
• -40 to 85°C operation
• CMOS 0.13 Micron Technology
• 1.8 and 3.3 Volt Power Supply
• 6 x 6 mm2 PBGA package with RoHS compliant lead free option
• ESD - 1500 V, 500 V High Speed Inputs

APPLICATIONs
• 10 G Fibre Channel and Ethernet Designs
• 10 GbE with FEC
• 10 G SONET/SDH/FEC Designs
• SONET/SDH Test Equipment
• SONET/SDH/FEC DWDM Equipment
• XFP MSA Modules