DFPCOMP Datasheet PDF - Digital Core Design

OVERVIEW
   O V E R V I E W The DFPCOMP compares two arguments. The input numbers format is according to IEEE-754 standard. DFPCOMP supports single precision real numbers. Compare operation was pipelined up to 1 level. Input data are fed every clock cycle. The first result appears after 1 clock period latency and next results are available each clock cycle. Full IEEE-754 unordered compare function is included.

KEY FEATURES
● Full IEEE-754 compliance
● Single precision real format support
● Simple interface
● No programming required
● 1 level pipeline
● Results available at every clock
● Fully configurable
● Fully synthesizable, static synchronous design with no internal tri-states

APPLICATIONS
● Math coprocessors
● DSP algorithms
● Embedded arithmetic coprocessor
● Data processing & control