HCTL-2021 Datasheet PDF - Avago Technologies

Description
The HCTL-2021/2017 is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2021/2017 consists of a quadrature decoder logic, a binary up/down state counter, and an 8-bit bus interface.

FEATUREs
• Interfaces Encoder to Microprocessor
• 33 MHz Clock Operation
• High Noise Immunity:
   Schmitt Trigger Inputs and Digital Noise Filter
• 16-Bit Binary Up/Down Counter
• Latched Outputs
• 8-Bit Tristate Interface
• 8 or 16-Bit Operating Modes
• Quadrature Decoder Output Signals, Up/Down and Count
• Cascade Output Signals, Up/Down and Count
• Substantially Reduced System Software
• 5V Operation (VDD – VSS)
• TTL/CMOS Compatible I/O
• Operating Temperature: -40°C to 85°C
• 16-pin and 20-Pin Launch Pad

APPLICATIONs
• Interface Quadrature Incremental Encoders to Microprocessors
• Interface Digital Potentiometers to Digital Data Input Buses