HYB25D128800CTL-6 Datasheet PDF - Infineon Technologies

Description
   The 128 Mbit Double Data Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.
   The 128 Mbit Double Data Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128 Mbit Double Data Rate SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

FEATUREs
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 2, 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8 µs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
• V
DDQ = 2.5 V ± 0.2 V (DDR266A, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400)
• VDD = 2.5 V ± 0.2 V (DDR266, DDR333); VDD = 2.6 V ± 0.1 V (DDR400)
• P-TFBGA-60-2 package with 3 depopulated rows (12 × 8 mm2)
• P-TSOPII-66-1 package
• Lead- and halogene-free = green product