ICS570AI Datasheet PDF - Integrated Circuit Systems

Description
The ICS570 is a high-performance Zero Delay Buffer (ZDB) which integrates ICS’ proprietary analog/digital Phase Locked Loop (PLL) techniques. The A version is recommended for 5 V designs and the B version for 3.3 V designs.

FEATUREs
• 8-pin SOIC package
• Available in Pb (lead) free package (A and B versions
   only)
• Pin-for-pin replacement and upgrade to ICS570M
• Functional equivalent to AV9170 (not a pin-for-pin
   replacement)
• Low input to output skew of 300 ps max (>60 MHz
   outputs)
• Ability to choose between 14 different multipliers
   from 0.5x to 32x
• Output clock frequency up to 168 MHz at 3.3 V
• Can recover degraded input clock duty cycle
• Output clock duty cycle of 45/55
• Power Down and Tri-State Mode
• Passes spread spectrum clock modulation
• Full CMOS clock swings with 25 mA drive capability
   at TTL levels
• Advanced, low power CMOS process
• ICS570B has an operating voltage of 3.3 V (±5%)
• ICS570A has an operating voltage of 5.0 V (±5%)
• Industrial temperature version available