ICS9179BF-01 Datasheet PDF - Integrated Circuit Systems

General Description
The ICS9179B-01 generates SDRAM clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Pentium II. An output enable is provided for testability.
The device is a buffer with low output to output skew. This is a Fanout buffer device, not using an internal PLL. This buffer can also be a feedback to an external PLL stage for phase synchronization to a master clock.
The individual clock outputs are addressable through I2C to be enabled, or stopped in a low state for reduced EMI when the lines are not needed.

FEATUREs
• High speed, low noise non-inverting (0:17) buffer for SDRAM clock buffer applications.
• Supports up to four SDRAM DIMMS
• Synchronous clocks skew matched to 250ps window on SDRAM.
• I2C Serial Configuration interface to allow individual clocks to be stopped.
• Multiple VDD, VSS pins for noise reduction
• Tri-state pin for testing
• Custom configurations available
• 3.0V - 3.7V supply range
• 48-pin SSOP package