LE82Q35SLJA7 Datasheet PDF - Intel

Introduction
The Intel® 3 Series Chipsets are designed for use with the Intel® Core™2 Duo desktop processor and Intel® Core™2 Quad processor based platforms. Each chipset contains two components: GMCH (or MCH) for the host bridge and I/O Controller Hub 9 (ICH9) for the I/O subsystem. The 82Q33 GMCH is part of the Intel® Q35 Express chipset. The 82Q33 GMCH is part of the Intel® Q33 Express chipset. The 82G33 GMCH is part of the Intel® G33 Express chipset. The 82P35 MCH is part of the Intel® P35 Express chipset. The ICH9 is the ninth generation I/O Controller Hub and provides a multitude of I/O related functions. The following figures show example system block diagrams for the Intel® Q35, Q33, G33 and P35 Express chipsets.

This document is the datasheet for the Intel® 82Q35, 82Q33, and 82G33 Graphics and Memory Controller Hub (GMCH) and Intel® 82P35 Memory Controller Hub (MCH). Topics covered include; signal description, system memory map, PCI register description, a description of the (G)MCH interfaces and major functional units, electrical characteristics, ballout definitions, and package characteristics.