LMU112JC25 Datasheet PDF - LOGIC Devices

DESCRIPTION
The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K.

FEATURES
❑ 25 ns Worst-Case Multiply Time
❑ Low Power CMOS Technology
❑ Replaces Fairchild MPY112K
❑ Two’s Complement or Unsigned Operands
❑ Three-State Outputs
❑ Package Styles Available:
    • 48-pin PDIP
    • 52-pin PLCC, J-Lead