M68Z128 Datasheet PDF - STMicroelectronics

DESCRIPTION
The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible.

■ ULTRA LOW DATA RETENTION CURRENT
    – 10nA (typical)
    – 2.0µA (max)
■ OPERATION VOLTAGE: 5V ±10%
■ 128Kb x 8 VERY FAST SRAM with OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIMES: 55ns
■ LOW VCC DATA RETENTION: 2V
■ TRI-STATE COMMON I/O
■ LOW ACTIVE and STANDBY POWER
■ AUTOMATIC POWER-DOWN WHEN DESELECTED
■ INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER® CONTROLLERS