M68Z512 Datasheet PDF - STMicroelectronics

DESCRIPTION
The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible.

FEATURES SUMMARY
■ ULTRA LOW DATA RETENTION CURRENT
    – 100nA (typical)
    – 10µA (max)
■ OPERATION VOLTAGE: 5.0V ± 10%
■ 512 Kbit x 8 SRAM WITH OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIMES: 70ns
■ LOW VCC DATA RETENTION: 2.0V
■ TRI-STATE COMMON I/O
■ CMOS FOR OPTIMUM SPEED/POWER
■ AUTOMATIC POWER-DOWN WHEN DESELECTED
■ INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER® CONTROLLERS