MG64P Datasheet PDF - Oki Electric Industry

DESCRIPTION
Oki’s 0.25 µm MG63P/64P/65P Application-Specific Integrated Circuit (ASIC) provides the ability to embed large blocks of Synchronous DRAM (SDRAM) into an embedded array architecture called the Customer Structured Array (CSA). Utilizing Oki’s leadership in DRAM technologies and wide experience of embedding SDRAM in logic products, Oki is able to integrate SDRAM and ASIC technology. The merged DRAM/ASIC process efficiently implements the Oki stacked capacitor memory cell. The MG63P/64P/65P CSA series uses three, four, and five metal process layers, respectively, on 0.25 µm drawn (0.18 µm L-effective) CMOS technology. The semiconductor process is adapted from Oki’s production-proven 64- Mbit DRAM manufacturing process.

FEATURES
• 0.25µm drawn 3-, 4-, and 5-layer metal CMOS
• Optimized 2.5-V core
• Optimized 3-V I/O
• CSA architecture availability
• 100 MHz embedded SDRAM cores up to 16 Mb  per occurrence
• 77-ps typical logic gate propagation delay (for a  4x-drive inverter gate with a fanout of 2 and 0  mm of wire, operating at 2.5 V)
• Over 5.4M raw gates and 868 I/O pads using  60µ staggered I/O
• User-configurable I/O with VSS, VDD, TTL,  3-state, and 1- to 24-mA options
• Slew-rate-controlled outputs for low-radiated  noise
• H-clock tree cells which reduces the maximum  skew for clock signals
• Low 0.2µW/MHz/gate power dissipation
• User-configurable single- and dual-port  memories (SRAM)
• Specialized IP cores and macrocells including  32-bit ARM7TDMI CPU, phase-locked loop  (PLL), and peripheral component interconnect  (PCI) cells
• Floorplanning for front-end simulation, back-end layout controls, and link to synthesis
• Joint Test Action Group (JTAG) boundary scan  and scan path Automatic Test Pattern  Generation (ATPG)
• Support for popular CAE systems including  Cadence, IKOS, Mentor Graphics, Model  Technology, Inc. (MTI), Synopsys, and  Viewlogic