ML688T Datasheet PDF - LANSDALE Semiconductor Inc.

Dual J-K Flip-Flop

   The negative–edge–clocked dual J-K flip-flop operates on the master–slave principle. His device provides both SET and RESET inputs on both flip-flops in the package. Each flip-flop may be set or reset by applying a low level to that particular input when the clock is low.
   The J and K inputs are inhibited when the clock is low and enabled when the clock is high. The logical state of the J and K inputs MUST NOT be allowed to change when the clock is in the high state.