MPC9600 Datasheet PDF - Integrated Device Technology

Low Voltage, 2.5V and 3.3V LVCMOS PLL Clock Driver

The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL based clock driver and fanout buffer. With output frequencies up to 200 MHz and output skews of 150 ps, the device meets the needs of the most demanding clock tree applications.

FEATUREs
• Multiplication of Input Frequency by 2, 3, 4, and 6
• Distribution of Output Frequency to 21 Outputs Organized in Three Output Banks: QA0-QA6, QB0-QB6, QC0-QC6, Each Fully Selectable
• Fully Integrated PLL
• Selectable Output Frequency Range Is 50 to 100 MHz and 100 to 200 MHz
• Selectable Input Frequency Range Is 16.67 to 33 MHz and 25 to 50 MHz
• LVCMOS Outputs
• Outputs Disable to High Impedance (Except QFB)
• LVCMOS or LVPECL Reference Clock Options
• 48-Lead QFP Packaging, Pb-Free
• ±50 ps Cycle-to-Cycle Jitter
• 150 ps Maximum Output-to-Output Skew
• 200 ps Maximum Static Phase Offset Window
• NRND – Not Recommend for New Designs