NB3N4666C Datasheet PDF - ON Semiconductor

Description
   The NB3N4666C is a quad−channel LVDS line receiver/translator offering data rates up to 400 Mbps (200 MHz) and low power consumption. The NB3N4666C receiver incorporates input fail−safe protection circuit that provides a known output voltage under input open−circuit and terminated (100 ) conditions. The four independent inputs accept differential signals such as: M−LVDS, LVDS, LVPECL and HCSL and translates them to a single−ended, 3.3 V LVCMOS.

FEATUREs
• Accepts M−LVDS, LVDS, LVPECL and HCSL Differential Input
   Signal Levels
• Maximum Data Rate of 400 Mbps
• Maximum Clock Frequency of 200 MHz
• 25 ps Typical Channel−to−Channel Skew
• 3.3 ns Maximum Propagation Delay
• 3.3 V ±10% Power Supply
• High Impedance Outputs When Disabled
   ✦ Low Quiescent Power < 10 mW Typical
• Supports Open and Terminated Input Fail−safe
• −40°C to +85°C Ambient Operating Temperature
• 16−Pin TSSOP, 5.0 mm x 4.4 mm x 1.2 mm
• These are Pb−Free Devices

APPLICATIONs
• Point−to−point Data Transmission
• Backplane Receivers
• Clock Distribution Networks
• Multidrop Buses